In many types of electronic systems, electronic components within the system may be capable of transmitting digital data to and receiving digital data from other components. For example, one device coupled to a bus may transmit data to another device on the bus. The data may be transferred in a series of data “phases” or “packets.” A finite amount of time is generally required for a data packet to be transferred from a source device to a destination device. Such time may be referred to as latency. Electronic system designers generally try to reduce the amount of latency in a system.
For various reasons, one or more of the bits comprising the data transmission may be received incorrectly. That is, a logic “0” may be received as a logic “1,” and vice versa. Such errors may have a detrimental effect on the operation of the system. Error detection and correction logic may be included but undesirably may add to the latency associated with data transfers in the system. It is thus desirable to implement an error detection and correction scheme and, in particular, an error detection and correction scheme that avoids or at least reduces the amount of added latency in the system.